Many semiconductor designs, both in Integrated Circuit (IC) and in Field Programmable Gate Array (FPGA) applications are constructed in a modular fashion by combining a set of IP cores, such as Central Processing Units (CPUs), Digital Signal Processors (DSPs), video and networking processing blocks, memory controllers and others with an interconnect system. The interconnect system implements the system-level communications of the particular design. The IP cores are typically designed using a standard IP interface protocol, either public or proprietary. These IP interface protocols are referred to as transaction protocols. An example transaction protocol is Open Core Protocol (OCP) from OCP-IP, and Advanced Extensible Interface (AXI™) and Advanced High-performance Bus (AHB™) from Arm Inc. As semiconductor designs have evolved from relatively small, simple designs with a few IP cores into large, complex designs which may contain hundreds of IP cores, the IP core interconnect technology has also evolved.
The first generation of IP core interconnect technology consisted of a hierarchical set of busses and crossbars. The interconnect itself consists mostly of a set of wires, connecting the IP cores together, and one or more arbiters which arbitrate access to the communication system. A hierarchical approach is used to separate high-speed, high performance communications from lower-speed, lower performance subsystems. This solution is an appropriate solution for simple designs. A common topology used for these interconnects is either a bus or a crossbar. The trade-off between these topologies is straightforward. The bus topology has fewer physical wires which saves area and hence cost, but it is limited in bandwidth. The wire-intensive crossbar approach provides a higher aggregate communication bandwidth.
The above approach has a severe limitation in that the re-use of the IP cores is limited. The interfaces of all the IP cores connecting to the same interconnect are required to be the same. This can result in the re-design of the interface of an IP core or the design of bridge logic when a particular IP core needs to be used in another system.
This first generation of interconnect also implements a limited amount of system-level functions. This first generation of IP core interconnect technology can be described as a coupled solution. Since the IP interfaces are logically and physically not independent from each other, they are coupled such that modifying one interface requires modifying all the interfaces.
The second generation of IP interconnect is a partially decoupled implementation of the above described bus and crossbar topologies. In these solutions, the internal communication protocol of the communications system, or transport protocol, is decoupled from the IP interface protocol, or transaction protocol. These solutions are more flexible with regards to IP reuse as in these solutions the semiconductor system integrator can connect IP cores with different interfaces to the same communication system through some means of configurability.
The third generation of IP core interconnect technology is the NoC, which implements not only decoupling between transaction and transport layers, but also a clean decoupling between transport and physical layers. The key innovation enabling this solution is the packetization of the transaction layer information. The command and data information that is to be transported is encapsulated in a packet and the transport of the packet over the physical medium is independent of the physical layer. The packet format consists of a header and a payload. The payload contains the data and data-related qualifiers such as byte-enable signals. The header contains routing information, system-level address, and additional control information such as security-related indicators. In this architecture, the NoC is constructed by connecting a set of IP elements such as network interface units, switches, synchronizers, width converters together through physical links. The elements are selected and connected in such a manner as to meet protocol, performance, Quality-of-Service (QoS), area and timing requirements of the System-on-Chip (SoC).
One challenge in the design of on-chip-interconnect and NoC technology is the requirement to meet the QoS requirements of the IC. Each data-flow from initiator to target has its own bandwidth and latency requirement to be met by the on-chip-interconnect. Certain traffic, such as from CPU to DRAM Controller has a low latency constraint. Other traffic, such as the traffic originating from a video-processing block has a bandwidth constraint that is driven by the “real-time” nature of the data stream. Other traffic may exhibit a burst-like behavior, that is, the traffic intermittently requires a high bandwidth access to a target resource.